1. Field of the Invention
The present invention relates to a method of forming a metal oxide semiconductor on a semiconductor wafer, and more particularly, to a method of forming a spacer of a metal oxide semiconductor on a semiconductor wafer.
2. Description of the Prior Art
A gate, a drain and a source comprise a MOS transistor. The performance of the MOS transistor depends on the structure of the gate and its spacer. During the general method of forming the MOS transistor, the gate is formed on the silicon substrate of a semiconductor wafer first, and then two spacers are formed on the two vertical sides of the gate. An ion implantation process is performed to form a drain and source on the silicon substrate outside the gate, with the gate and spacers serving as a mask during the process. However, with critical dimension reductions, the prior art formation of the spacer is no longer satisfactory, adversely affecting the quality of the resulting semiconductor devices.
Please refer to FIG. 1 to FIG. 5. FIG. 1 to FIG. 4 are schematic diagrams of the prior art formation of a MOS transistor 20. The prior art formation of the MOS transistor 20 is performed on a semiconductor wafer 10. As shown in FIG. 1, the semiconductor wafer 10 comprises a silicon substrate 12, a dielectric layer 14 positioned on the silicon substrate 12 to serve as a gate oxide layer, and a gate 16 with at least two vertical sides positioned on a predetermined region of the dielectric layer 14. Each gate 16 comprises a conductive layer 11 positioned on the predetermined region of the dielectric layer 14, a silicide layer 13 positioned above the conductive layer 11 to reduce the interface resistance of the conductive layer 11, a passivation layer 15 positioned above the silicide layer 13, and an anti-reflection coating (ARC) layer 17 positioned above the passivation layer 15. The dielectric layer 14 is made of silicon oxide, the conductive layer 11 is made of doped poly-silicon, the silicide layer 13 is made of tungsten silicide (WSi), the passivation layer 15 is made of silicon nitride and the ARC layer 17 is made of silicon nitride oxide (SiON).
As shown in FIG. 2, a silicon oxide layer 18, 100 .ANG. thick, is formed on the semiconductor wafer 10, uniformly covering the gate 16 and the dielectric layer 14. Then, a first ion implantation process is performed to form two first doped regions 22 that function as the lightly doped drain of the MOS transistor 20. Next, a silicon nitride layer 24 is uniformly formed on the semiconductor wafer 10, entirely covering the silicon nitride layer 18.
As shown in FIG. 3, an anisotropic dry etching process is performed to vertically remove both the silicon nitride layer 24 and the silicon oxide layer 18 above the gate 16. The remaining silicon nitride layer 24 on the vertical sides of the gate 16 becomes a spacer 25. As shown in FIG. 4, finally, a second ion implantation process is performed to dope the silicon substrate 12 not covered by the spacers 25. This forms a second doped region 26 under the first doped region 22 that functions as the source and drain of the MOS transistor 20.
In the prior art method, during the dry etching process to form the spacers 25, a portion of the dielectric layer 14 between two spacers 25 will also be etched. Therefore, during the second ion implantation process, the thickness of the dielectric layer 14 will not be sufficient enough to protect the silicon substrate 12. Consequently, the surface of the silicon substrate will become very rugged.
Furthermore, the vertical sides of the gate 16 of the MOS transistor 20, covered with the silicon oxide layer 18, are vulnerable to short-circuiting when forming a subsequent contact plug 29. Please refer to FIG. 5. FIG. 5 is a cross-sectional diagram of the contact plug 29 of the MOS transistor 20 shown in FIG. 4. After the MOS transistor 20 is completed, the contact plug 29 must be formed on the semiconductor wafer 10 so that the MOS transistor 20 has an electrical connection with a subsequent metal layer (not shown). The prior art method comprises depositing another dielectric layer 27 on the semiconductor wafer 10, performing a self-aligned etching process to form a contact hole 28, and filling dielectric material into the contact hole 28 to form the contact plug 29. However, during the etching process, if the position of the contact hole 28 is not precisely defined, the silicon oxide layer 18 on the vertical sides of the gate 16 may also be etched, resulting in short-circuiting between the gate 16 and the contact plug 29.